1. Field of the Invention
The present invention relates generally to semiconductor fabrication, and more particularly to semiconductor fabrication methods for reducing spacing dimensions or pitch between features.
2. Description of Related Art
Integrated circuits are in wide use today. A typical integrated circuit includes electronic devices electrically connected by conductive interconnect lines (i.e., interconnects). Interconnects are typically patterned from conductive layers formed on or above the surface of a semiconductor wafer. One or more conductive layers may be patterned to form one or more levels of interconnects, spaced from each other by one or more interlevel dielectric structures.
Integrated circuits including metal oxide semiconductor (MOS) transistors can offer performance advantages over circuits including other types of active electronic devices (e.g., bipolar transistors) in many applications. MOS transistors are formed in and on semiconductor wafers, and typically within defined active regions of major wafer surfaces.
In integrated circuits formed on silicon wafers, polycrystalline silicon (i.e., polysilicon) is commonly used to form interconnects, including gate electrodes of MOS transistors. The use of polysilicon to form the gate electrodes of MOS transistors allows source and drain regions of the MOS transistors to be precisely defined in for example a self-aligned process. In the self-aligned process, overlaps between the gate electrodes and source and drain regions can be minimized, improving MOS transistor (and circuit) performance.
When polysilicon is used to form gate electrodes in MOS transistors, undoped polysilicon is typically deposited on a gate insulator layer. The gate insulator layer is typically silicon dioxide (SiO2); thus the gate insulator layer is commonly referred to as a gate oxide layer.
In a typical self-aligned process, a thin, highly controlled layer of silicon dioxide (i.e., oxide) is grown on exposed surfaces of a silicon wafer in defined active areas of the silicon wafer. Polysilicon is deposited over the entire semiconductor wafer, and patterned to form desired interconnect features, including gate electrodes. Portions of the gate oxide not covered by the polysilicon features are etched away, and the silicon wafer is exposed to a dopant source. As a result, dopant atoms are implanted in the silicon wafer (i.e., substrate), forming diffusion junctions in the substrate. The diffusion junctions form the source and drain regions of MOS transistors. Dopant atoms are also implanted in the polysilicon features (i.e., the polysilicon features are also doped). The doping of the polysilicon features reduces the resistivity of the polysilicon features, increasing the electrical conductivity of the polysilicon features.
In the above described self-aligned process, the drain and source regions are formed only in regions of the substrate not covered by the polysilicon gate electrode features. The source and drain regions do not extend under the polysilicon gate electrodes. The gate/source/drain overlaps are minimized, and MOS transistor (and circuit) performance can be improved.
Integrated circuit features are typically formed by patterning sheets or layers of desired materials via a lithographic process (e.g., photolithography). During lithographic processes, undesired portions of layers of desired materials are removed (e.g., via etching). The remaining desired portions define features including the desired materials.
In integrated circuits, as in circuits in general, conductive features (e.g., interconnects) must be isolated from one another to prevent electrical contact, and to reduce electrical capacitance and signal cross talk. The term xe2x80x9cpitchxe2x80x9d is commonly used to refer to a distance between a reference point (e.g., an edge, a center point, etc.) of a feature, and a corresponding point of an adjacent, similar feature. In general, pitches which achieve acceptable levels of performance are specified during design of an integrated circuit, and maintained during fabrication of the integrated circuit.
Integrated circuits are generally categorized by critical dimensions (i.e., sizes) of electronic devices, and/or densities of electronic devices per unit area (i.e., levels of device integration). In order to obtain higher levels of performance, the trend in the semiconductor fabrication is toward smaller electronic devices and denser integrated circuits (i.e., higher levels of device integration). Making integrated circuits denser necessarily entails reducing pitches between conductive features. Limits of lithographic processes used to form features typically determine critical dimensions (i.e., sizes) of electronic devices, as well as minimum spacing distances between the features. In general, integrated circuit features, including conductive features, are typically arranged as close to one another as the limits of the lithographic process used to form the features will permit.
In order to increase the density of electronic devices per unit area (i.e., achieve higher levels of device integration), an ongoing need exists to reduce spacing distances between adjacent features of integrated circuits, and pitches between conductive features.
A method is described which may be used to reduce a pitch between conductive features. One embodiment of the method involves forming a structure including a substrate, a conductive layer on the substrate, multiple photoresist features arranged on the conductive layer, a polymer layer on sidewalls of each of the photoresist features, and a material layer on and around the photoresist features and the polymer layers. An upper portion of the material layer is removed such that upper surfaces of the photoresist features and the polymer layers are exposed, and a remaining portion of the material layer remains. The polymer layers are removed, and the photoresist features and the remaining portion of the material layer are used as etch masks to pattern the conductive layer, thereby producing a plurality of conductive features. The photoresist features and the remaining portion of the material layer can then be removed.
The material layer may be formed from a material that is volatilized at a temperature greater than a temperature at which a polymer material making up the polymer layers is volatilized. Further, the photoresist layer may be formed from a resist material that is volatilized at a temperature greater than a temperature at which a polymer material making up the polymer layers is volatilized. In this situation, the polymer material making up the polymer layers may be removed by volatilizing it in an ashing chamber at a temperature low enough that the remaining portion of the material layer and the photoresist features are substantially unaffected. In addition to sidewalls, the polymer layer can be also be formed on top surfaces of the photoresist features.
In situations where the photoresist features are formed using a photolithographic process, and the pitch of the photoresist features is as small as the photolithographic process will allow, the conductive features produced using the above method may be approximately half of the pitch of the photoresist features. The resulting decrease in the pitch between conductive features allows more electronic devices per unit area of semiconductor substrate (i.e., higher levels of device integration).
Any feature or combination of features described herein are included within the scope of the present invention provided that the features included in any such combination are not mutually inconsistent as will be apparent from the context, this specification, and the knowledge of one of ordinary skill in the art. Additional advantages and aspects of the present invention are apparent in the following detailed description and claims.